VPN overall performance

2002; Hifn 2003; Wang et al. 2006). The main components include the cryptographicengines, 32-bit data bus, cryptochannels and PCI interface, in which each part isconnected to the others by a bidirectional data transfer path. The system architecturewas meant to establish a parallel computational array; however, the 32-bitbidirectional data bus and the PCI interface become bottlenecks of the data transferefficiency. Because the bidirectional data bus performs both data read and writeoperations, bus contentions are inevitable and a tremendous amount of arbitrationsare needed. The data could still become congested along the data transfer path eventhough arbitrated. Moreover, the system specifies that the cryptochannels are incharge of the data transfer between the crypto engines and external memories via thePCI interface, so a complete data transfer path cannot be set up until onecryptochannel obtains control of the PCI interface and the designated crypto engineat the same time. Hence, data transfer latency is prolonged and the overall systemperformance with this architecture is severely degraded. Furthermore, a cryptochannel works as a subcontroller which controls the crypto engines from the dataimport stage to data processing until the processed data is exported; thus, thenumber of parallel processing tasks is limited by the number of cryptochannels,which significantly degrades the overall performance and system extensibility. Thearchitecture can be improved by changing the critical data transfer path in the databus and the PCI interface using a pipeline methodology by reducing cryptochannelsfrom subcontrollers to DMA arrays. As shown in Figure 2(b), the optimised systemdata transfer path is changed from a bidirectional 32-bit bus to dual one-way 64-bitdata buses to significantly reduce data congestion and arbitration. One-way DMAarrays are implemented to work with one-way data buses, including config directmemory access (CDMA), write direct memory access (WDMA) and read directmemory access (RDMA) arrays that transfer configuration and data information,respectively. Furthermore, a five-stage-pipeline is implemented through the datatransfer path to improve the usage efficiency of the PCI-X interface and increase thedata transfer rate. These changes greatly enhance the data transfer efficiency and